**Nominal frequency:**

The center or nominal frequency of a crystal oscillator.

**Frequency stability:**

Deviation from the nominal output frequency including the frequency deviation due to manufacturing process, temperature, power source variation and load variation. The most common stabilities are±25, ±50 and ±00ppm.

**Operating temperature range**

Temperature range within which output frequency stability and other electrical, Environmental characteristics meet the specifications. Military: -55℃ to+125℃; Industrial:-40℃ to+85℃;commercial: 0℃ to+70℃.

**Frequency aging:**

The relative frequency change over a certain period of time. The rate of change ofFrequency is normally exponential in character. Typically, aging is ±5 ppm maximum over 1 year.

**Storage temperature:**

The temperature range within which the unit is safely stored without damaging orChanging the performance of the unit.

**Oscillator output:**

The output of a hybrid crystal oscillator is a highly stable reference signal and it can formsquare wave of HCMOS or TTL level, depending on the technology of the active devices used in the circuit.Output logic: The vast majority of systems require a crystal oscillator output that is TTL compatible, CMOSCompatible, ECL compatible or some combinations of logic families such as TTL/HCMOS compatible.

**TTL/HCMOS compatible:**

The oscillator is designed with ACMOS logic with driving capability of TTL andHCMOS loads while maintaining minimum logic HIGH of the HCMOS.

**Logic levels:**

Logic levels may be positive or negative. Positive logic is assumed when logic 1 level is morePositive than logic 0 level, while negative logic is assumed when the logic 1 level is more negative than logic 0 Level.

**Output HIGH voltage (VOH):**

The minimum voltage at output logic 1 state of the oscillator under properLoading.

**Output LOW voltage (VOL):**

The maximum voltage at output logic 1 state of the oscillator under properLoading.

**Fan out (Loads):**

The measure of the driving capability of an oscillator, expressed as the number of inputs thatcan be driven by a single output. It can be represented by an equivalent load capacitance specified at pF inCMOS logic or the number of gates in TTl load circuit consisting of diode, load resistors, and a capacitor. If This value exceeds the maximum rated load of the oscillator, signal degradation can occur.

**Startup time:**

The startup time is specified as the that an oscillator take to reach its specified RF output amplitude. The startup time is determined by the closed loop time constant and the loading condition of its circuit.

**Rise & Fall time (Tr & Tf):**

The rise time Tr of an oscillator is defined as the transition time of the output waveform from low stage (logic 0 ) to high stage (logic 1 ). The fall time Tf of an oscillator is defined as the transition time of the output waveform from high stage (logic 1 ) to low stage (logic 0 ). The transition times measured at the specified level such as between 90% and 10% of the falling edge of the switching waveform for HCMOS device. Increasing the load will increase the rise and fall times of the device.

**Symmetry or Duty cycle:**

The measure of output waveform uniformity of the shape of the waveform, which is made up of logic 1 and logic 0 cycle times. It is defined as the ratio of the time periods of the logic 1 level (TH) to the time periods of one complete cycle (T), measured at 1.4 volts for TTL logic and 50% of the peak-to-peak voltage for CMOS. Sym=TH/T X 100%.

**Tri-state enable:**

By applying a command input signal to the oscillators, the output of the clock oscillators is turned off or disabled. When this feature is activated, the oscillators assume a high impedance state. This feature allows the oscillator to be isolated from the circuit upon application of a command signal.

**Input current ad supply voltage:**

Input current is the amount of current deain by an oscillator in its operating condition. Different logic oscillators require different input current. Supply voltage is the voltage necessary to operate the oscillator. It is typically 5 V or 3.3 V.

**Phase Noise:**

Phase noise is a small fraction of undesirable frequency near the output frequency, and is usually Expressed as the single side band (SSB) power density density in a 1 Hz bandwidth at a specified oddest frequency from The carrier. It is measure in dBc/Hz.

**Jitter:**

Measure of the modulation in phase or frequency of the oscillator output.

**Standby function:**

A function built in the IC that temporary turns off the oscillator to save power. Logic 0 will enable stand by mode. The disable current at stand by mode varies from few micro ampered to tens of micro amperes (0.005 mA typical). Because oscillation is halted, there is a maximum of 10ms (same amount as the start-up time) before output stabilizes.

**Harmonic distortion:**

The non-linear distortion due to un-wanted harmonic spectrum component related with Target signal frequency. Each harmonic componic component is the ratio of electric power against desired signal outputelectric power and expressed in terms of dBc. The non-linear distortion due to un-wanted harmonic spectrum component related with Target signal frequency. Each harmonic componic component is the ratio of electric power against desired signal outputelectric power and expressed in terms of dBc.

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